JPS62214648A - 半導体素子用パツケ−ジの製造方法 - Google Patents

半導体素子用パツケ−ジの製造方法

Info

Publication number
JPS62214648A
JPS62214648A JP5769886A JP5769886A JPS62214648A JP S62214648 A JPS62214648 A JP S62214648A JP 5769886 A JP5769886 A JP 5769886A JP 5769886 A JP5769886 A JP 5769886A JP S62214648 A JPS62214648 A JP S62214648A
Authority
JP
Japan
Prior art keywords
conductive paste
ceramic green
green sheet
semiconductor element
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5769886A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0459778B2 (en]
Inventor
Takeshi Suzuki
剛 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NGK Insulators Ltd
Original Assignee
NGK Insulators Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NGK Insulators Ltd filed Critical NGK Insulators Ltd
Priority to JP5769886A priority Critical patent/JPS62214648A/ja
Publication of JPS62214648A publication Critical patent/JPS62214648A/ja
Publication of JPH0459778B2 publication Critical patent/JPH0459778B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP5769886A 1986-03-15 1986-03-15 半導体素子用パツケ−ジの製造方法 Granted JPS62214648A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5769886A JPS62214648A (ja) 1986-03-15 1986-03-15 半導体素子用パツケ−ジの製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5769886A JPS62214648A (ja) 1986-03-15 1986-03-15 半導体素子用パツケ−ジの製造方法

Publications (2)

Publication Number Publication Date
JPS62214648A true JPS62214648A (ja) 1987-09-21
JPH0459778B2 JPH0459778B2 (en]) 1992-09-24

Family

ID=13063155

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5769886A Granted JPS62214648A (ja) 1986-03-15 1986-03-15 半導体素子用パツケ−ジの製造方法

Country Status (1)

Country Link
JP (1) JPS62214648A (en])

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5067007A (en) * 1988-06-13 1991-11-19 Hitachi, Ltd. Semiconductor device having leads for mounting to a surface of a printed circuit board
US5094969A (en) * 1989-09-14 1992-03-10 Litton Systems, Inc. Method for making a stackable multilayer substrate for mounting integrated circuits

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5816552A (ja) * 1981-07-22 1983-01-31 Fujitsu Ltd 半導体素子用パッケ−ジ
JPS5851544A (ja) * 1981-09-22 1983-03-26 Fujitsu Ltd 半導体装置のパツケ−ジ

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5816552A (ja) * 1981-07-22 1983-01-31 Fujitsu Ltd 半導体素子用パッケ−ジ
JPS5851544A (ja) * 1981-09-22 1983-03-26 Fujitsu Ltd 半導体装置のパツケ−ジ

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5067007A (en) * 1988-06-13 1991-11-19 Hitachi, Ltd. Semiconductor device having leads for mounting to a surface of a printed circuit board
US5094969A (en) * 1989-09-14 1992-03-10 Litton Systems, Inc. Method for making a stackable multilayer substrate for mounting integrated circuits

Also Published As

Publication number Publication date
JPH0459778B2 (en]) 1992-09-24

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees